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Ashok Babu, K.
- Implementation of Test Data Compression For Huffman Decoder
Abstract Views :149 |
PDF Views:3
Authors
Affiliations
1 Department of Electronics & Communication Engineering, Sri Indu College of Engineering and Technology, Andhra Pradesh, IN
2 Department of Electronics & Communication Engineering, Sri Indu College of Engineering and Technology, Andhra Pradesh-10, IN
1 Department of Electronics & Communication Engineering, Sri Indu College of Engineering and Technology, Andhra Pradesh, IN
2 Department of Electronics & Communication Engineering, Sri Indu College of Engineering and Technology, Andhra Pradesh-10, IN
Source
Digital Signal Processing, Vol 2, No 10 (2010), Pagination: 189-195Abstract
Huge data system applications require storage of large volumes of data set, and the number of such applications is constantly increasing as the use of computers extends to new disciplines. At the same time, the proliferation of communication networks is resulting in massive transfer of data over communication links. Compressing data to be stored or transmitted reduces storage and communication costs. When the amount of data to be transmitted is reduced, the effect is that of increasing the capacity of the communication channel. Here efficient method for decoding the compressed data is proposed. This paper aims toward the implementation of a high speed Huffman decoding system. This proposed model enhances the speed of decoding operation. The model is implemented using VHDL language, simulated on Active HDL 5.1, synthesized, placed and routed and floorplaned using Xilinx tools.Keywords
Decoder, Simulation, Huffman Decoder.- High Speed Parallel Butterfly Architecture for Computing Circular Convolution Based on FNT Using Modulo 2n+1 Partial Product Multiplier
Abstract Views :158 |
PDF Views:4
Authors
Affiliations
1 Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, IN
1 Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, IN
2 Department of Electronics and Communication Engineering, Sri Indu College of Engineering and Technology, IN
Source
Digital Signal Processing, Vol 2, No 10 (2010), Pagination: 217-225Abstract
This paper presents high speed butterfly architecture for circular convolution based on FNT using partial product multipliers. FNT is ideally suited to digital computation requiring the order of N log N additions, subtractions and bit shifts, but no multiplications. In addition to being efficient, the FNT implementation is exact with no round off errors. Binary arithmetic permits the exact computation of FNT. This technique involves arithmetic in a binary code corresponding to the simplest one of a set of code translations from the normal binary representation of each integer in the ring of integer. In the first stage normal binary numbers are converted into their diminished-1 representation using code conversion (CC). Then butterfly operation (BO) is carried out to perform FNT and IFNT where the point wise multiplication is performed using modulo 2n+1 partial product multipliers. Thus modulo 2n+1 additions are avoided in the final stages of FNT and IFNT and hence execution delay is reduced compared to circular convolution done with FFT and DFT. This architecture has better throughput and involves less hardware complexity.Keywords
FNT, Code Conversion, Butterfly Operation, Diminished-1 Representation, Partial Product Multiplier.- Implementation of Test Data Compression for Huffman Decoder
Abstract Views :130 |
PDF Views:3
Authors
Affiliations
1 Department of Electronics & Communication Engineering, Sri Indu College of Engineering and Technology, Andhra Pradesh, IN
2 Department of Electronics & Communication Engineering, Sri Indu College of Engineering and Technology, Andhra Pradesh-10, IN
1 Department of Electronics & Communication Engineering, Sri Indu College of Engineering and Technology, Andhra Pradesh, IN
2 Department of Electronics & Communication Engineering, Sri Indu College of Engineering and Technology, Andhra Pradesh-10, IN